Semiconductor manufacturing technology is constantly changing and advancing to realize smaller feature sizes in manufacturing, thus permitting the manufacture of faster, more dense and power efficient electronic circuits. Semiconductor chips, such as application specific integrated circuit chips (“ASICs”) and custom logic chips, such as microprocessors and memories, are designed in this environment of change, often on short design schedules.
In order to utilize the latest changes and advances in semiconductor manufacturing technology for a particular chip design or designs, as well as to realize particular performance goals, such as low power and high-speed performance, the design process may often involve creating entirely new electronic circuits for every circuit on the chip or chips. This is challenging because modern chips are very complex, including millions of transistors and often a mile or more of wire interconnecting the transistors. In view of short design schedules and the complexity of chip designs, there is a substantial need for speed and accuracy during the chip design process and for systems to identify and correct design errors in newly designed electronic circuits prior to manufacturing.
One conventional way to improve the efficiency of the chip design process is through hierarchical design. Most, if not all chip designs include large numbers of groups of electronic circuits that perform an identical function. Therefore, it is convenient to identify these groups and design each group one time as a cell. The identical cells may then be instantiated many times on the chip during the design process to create the chip.
In hierarchical design, the lowest level of the design hierarchy is a cell conventionally called a “leaf cell.” The leaf cell is an electronic circuit implementing a particular function which includes only the fundamental circuit elements of the technology such as, for example, transistors, capacitors, inductors, resistors and diodes. Above the leaf cells in the design hierarchy are cells which may include other cells, leaf cells and/or fundamental circuit elements which are interconnected to realize a desired function. At the highest level of the design hierarchy, the entire chip is represented as interconnected cells in a single cell conventionally called a “root cell.” The root cell is analogous to the trunk of a tree, where each cell in the root cell is a branch off of the trunk of the tree. Each branch may include several levels of hierarchy between its interface with the trunk and the end of the branch, which is the leaf cell. The set of cells that are present in a chip design is generally referred to as a “library” and the set of leaf cells that are available for implementation in a chip design, are generally referred to as a “macro library” or “cell library.”
The chip design process generally includes a logic design process and physical design process. In the logic design process, schematics representing the electronic circuits that comprise individual cells of the chip, as well as the entire chip, are created at each level of the design hierarchy to realize particular functional and performance goals. In the physical design process, the schematics of individual electronic circuits are transformed into the corresponding geometric shapes of mask works that are used in manufacturing the chip. The physical design process generally seeks to take advantage of the latest advances in semiconductor manufacturing technology by using minimum feature sizes to implement circuit elements where appropriate.
The logical and physical design processes are facilitated by the use of design automation tools. Typically, design automation tools run on a computer workstation, such as a UNIX based workstation. For example, during the logical design process, design automation tools called logic synthesis tools allow a chip designer to create schematics for cells at any or all levels of the design hierarchy. In addition, once a cell library representing the available leaf cells has been designed, design automation tools allow designers to automatically create or “synthesize” a schematic for an entire chip, or a substantial portion thereof, from a functional representation of a chip. The logic synthesis tools use the leaf cells of the cell library as building blocks for the chip design.
During the physical design process, design automation tools allow the automatic generation of the geometric shapes of the mask works directly from schematics on a cell-by-cell basis. The latter is typically done in stages. For example, in one stage, a cell schematic is conventionally converted into geometric shapes called “layout” using a layout synthesis tool. The layout synthesis tool takes a cell schematic as input, and outputs a “symbolic layout” for the cell by converting each circuit element, such as a transistor, capacitor, resistor or diode, into predefined geometric shapes or symbols representing a manufacturing plan for the circuit element. The layout synthesis tool also preserves connectivity between the circuit elements represented as symbols in the layout. In a later stage, the symbolic layout of the cell is compacted into a smaller area than it originally occupied, typically based on manufacturing groundrules defined for the desired semiconductor manufacturing technology. The compaction process is designed to increase the density of electronic circuits to the maximum extent permitted by the manufacturing technology.
During a chip design, the creation of the logical and physical designs of the leaf cells or “cell library” is critically important as the macro library forms the basic building blocks for the chip. Once the physical design of the leaf cells is completed, then the physical design of the chip may proceed by placing instances of the leaf cells and other cells into the root cell of the chip and routing wires between the leaf cells as defined by the hierarchy of the root cell schematic. In addition, data generated from the physical design of the leaf cells, such as input pin capacitance, drive strength and delay, are used in chip simulation to verify proper operation and performance and to make final logical design changes in view of the chip simulation.
There are several shortcomings to applying available design automation tools to the task of creating physical designs for a cell library. For example, conventionally, the process of creating layout for individual cells requires substantial manual intervention for each cell. In particular, manual intervention is required to make leaf cells conform to an overall plan for the macro library, such as uniform form factors and power buses and the inclusion of substrate and well contacts in cells. In addition, conventional tools for checking the integrity of the physical design, such as logical to physical and design rule checking tools, are not exhaustive. Thus, conventional processes leave the possibility for flaws in the physical design of the chip.
There is a need for an improved system for automated chip design that allows macro libraries to be generated quickly and directly from leaf cell schematics without substantial manual intervention. There is a further need to apply constraints to design automation tools to facilitate generation of a macro library which conforms to an overall plan. There is still a further need for additional checking of leaf cells to ensure correctness of the physical design of the leaf cell library and, therefore, manufacturability.